Adaptive Image Size Padding for Load Balancing in System-on-Chip Memory Hierarchy

Abstract

The conventional address map often incurs traffic congestion in on-chip memory components and degrades memory utilization when the access pattern of an application is not matched with the address map. To reduce traffic congestion and improve the memory system performance, we propose an adaptive image size padding technique for a given address mapping and a hardware configuration. In the presented software approach, the system can adaptively determine the image pad size at the application-invoke time to enhance the load balancing across the on-chip memory hierarchy. Mainly targeting a high-bandwidth image processing application running in a device accelerator of an embedded system, we present the design, describe the algorithm, and conduct the performance experiment. As a result, the experiments indicate the presented design can improve load balancing up to 95% and performance up to 35%, with insignificant memory footprint overheads.