Adaptive Hybrid Transaction Processing with Hardware Transaction Memory

Abstract

Many performance-sensitive software systems gain benefit from the availability of advanced hardware features, and many research works have been transited to engineering reality. For instance, restricted hardware transaction memory (HTM), a hardware feature providing hardware atomicity and isolation guarantees for transactional execution, has gained much attention in the community of database system and becomes a new kind of approach for concurrency control of transaction processing. Previous works show that hardware transactional memory is a very promising mechanism when processing typical OLTP workloads and scales well on multi-core machines. However, the high transaction abort rate caused by capacity overflow is also the major trouble when applying hardware transactional memory in transaction execution under high-contention workloads. Many methods, such as falling back to lock-based approaches, have been proposed to improve the performance when applying hardware transactional memory to transaction execution. In this paper, we analyze the penalty of abort and fall back when hardware transactional memory fails to process transactions. Based on these analyses, we exploit the strengths of hardware transactional memory with an adaptive hybrid mechanism to improve both the throughput and latency of transaction processing on the multicore systems. Our experiment on TPC-C shows that our adaptive design can remarkably improve the throughput and latency of in-memory transaction processing.