Adaptive Feedback Mechanism for Silicon Bug Detection

Abstract

Silicon validation is the most time-consuming process in the VLSI design flow. It mainly involves pre-silicon validation and post silicon validation. Post-silicon validation has limited visibility and control of internal signals and is the most time-consuming task. To help in narrowing down the features responsible for failure and reproduce the bug, the power of machine learning is leveraged. Based on the data provided, machine learning is used to provide the feature weights that control the failure of the device, thereby leading to faster reproduction of the failure. The framework that stresses the CPU requires manual intervention for providing test vectors and hence to have a faster response, the framework is automated with a reset mechanism so that it can include tests that are expected to fail on the device. Based on sample data, the machine learning model using supervised learning algorithms is developed. Results show that the model is accurately able to predict the features responsible for failure when applied on real time chip data. Due to automation, there is about 66% saving in time when compared to the manual process, thereby giving more time for more experiments to be run on the device and faster time to market.