Adaptive dynamic voltage transitioning in switch mode DC–DC power converters

Abstract

Higher transistor density in modern processors leads to an increase in computing power, which results in higher power consumption. To combat this, system-level power saving features like dynamic voltage transitions (DVTs) are introduced where the voltage required by the processor is varied according to computational load. In commercially available systems, the slew rate of the voltage transition is limited, which has the negative effect of increasing computational latency to ensure safe operation of the switch mode power converter. This study addresses the limitations of the existing techniques by introducing an adaptive DVT, which enables finer granularity of the operating voltage levels and promotes greater power savings. The switching surface-based analysis is performed to derive the conditions for (near) optimal voltage transitions constrained by inductor saturation limits. The results of an experimental prototype achieving the fastest safe transition response are shown to correlate well with the analysis across a wide range of DVT conditions.