Adaptive droop-based SoC balancing control scheme for parallel battery storage system in shipboard DC microgrid

Abstract

In this article, an adaptive droop control strategy is proposed for parallel battery storage systems (BSSs) in shipboard DC microgrids, addressing critical challenges such as State-of-Charge (SoC) equilibrium, precise load power distribution, and regulation of DC bus voltage. In the primary control layer, an innovative adaptive droop-based SoC (ADBS) controller is introduced, leveraging SoC information with dynamic droop coefficient adaptation based on a sigmoid function. ADBS aims to stabilize SoC dynamically while ensuring accurate load current allocation among battery storage units (BSUs). A virtual voltage drop equalization controller (VVDE) is employed to mitigate the influence of line impedance mismatches, while a bus voltage compensation controller (BVC) is utilized to compensate for DC bus voltage deviation in the secondary control layer. Communication is established through a sparse network in the communication layer, where each BSU communicates exclusively with its adjacent BSUs. An iterative multi-agent consensus algorithm collectively estimates the average values of global variables for communication burden reduction and coordinated control efforts. Additionally, stability analysis for the suggested control approach is conducted. Finally, a simulation model (MATLAB/Simulink) and experimental platform (Star Sim HIL) have been developed to validate the strategy's effectiveness. The results of the proposed approach successfully attain dynamic SoC equilibrium, precise load current distribution, and DC bus voltage restoration in diverse environments, with notably faster SoC convergence compared to state-of-the-art methods. More importantly, through comparative analysis, it is evident that the presented approach demonstrates significantly superior performance. The SoC and current of each BSU have ultimately attained consistency, with errors approximately around 0 % and 0 A. In contrast, the comparison method yields errors of approximately 3 % and 1.02 A in the SoC and current of each BSU in the simulation results, and around 4 % and 2 A in the case of experimental results.. Finally, the proposed methodology offers a comprehensive solution, showcasing robust performance, adaptability, and superior control in diverse operating conditions.