Adaptive Control Methodology for High-performance Low-power VLSI Design

Abstract

Very Large Scale Integrated chip design consists of several steps including modeling characteristics of transistors, profiling circuit level behaviors, abstracting into gate level parameters, synthesizing logic based on timing constraints, and so on. The common concept that runs through all these sequence of design flow is modeling. Traditional VLSI design highly replies on the modeling process, and the percentage that a design chip is successful, or say yield, is determined by how much the modeling is done accurately and precisely. In order to increase the yield, designers put margins while they design. A designer assumes worst cases in design parameters like transistor speed, supply voltage, temperature, and operation frequency. Even though sufficient margin on those design parameters leads higher chance of success in chip design, the margins imply overhead on the other hand. The overhead costs additional power consumption, which should be conquered in this lowpower era. Another cause of such over-design is variable workload in a system. Most of traditional VLSI systems are designed to support the maximum possible workload and the system becomes to have headroom in terms of performance when the workload is not that high. Modern VLSI designs deploy the concept of adaptive control schemes to manage the costs caused by the over-designs. A chip embeds transistor speed meter, and temperature sensors to monitor actual environment that the chip is operating in, and adjusts the margins to be minimal in order to minimize the additional cost. According to the workload offered to the system, the system controls its supply voltage dynamically thus the system keeps its performance just as enough. In this chapter, we introduce the design cases that use adaptive control schemes to manage the overhead while reducing power consumption. One another factor causing over-design is uncertainty, which is emerged in recent VLSI design area. Huge complexity of system-on-chips and ever shrinking transistor size has brought the uncertainty issue in modern VLSI design. One example is clock synchronization issue. As the clock frequency goes beyond Giga-hertz, the chip area is no longer bounded within a single clock cycle, thus, clock synchronization in a chip became extremely challenging, and even impossible to achieve. The terminology, Network-on-Chip has begun to widely spread in the VLSI design field as a chip becomes a set of systems interconnected through a network. In such a big system, transmitting and receiving data signals involves timing uncertainty because it is no longer a synchronous system. Such uncertainty incurs