Adaptive Cache Line Strategy for Irregular References on Cell Architecture

Abstract

Software cache is a commonly used method which solves the irregular applications on Cell processor.Considering that software cache usually ignores the irregular reference memory access pattern and thus sets the cache line to a specific length,which elevates memory bandwidth overhead and limits cache utilization,this paper proposes an adaptive cache line strategy,which continuously adjusts cache line size during applications execution,therefore,the transferred data size is decreased significantly.Moreover,this paper presents a corresponding software cache—hybrid line size cache(HLSC).It introduces a hybrid Tag Entry Array,with each mapping to a different line size.It's a hierarchical design in that when a miss is occurred in the long line Tag Entry Array,misshandler is invoked at once.But if there is a miss in the short line Tag Entry Array,misshandler is invoked immediately as well the long line Tag Entry Array is checked.If it's a hit in the long line Tag Entry Array,misshandler is abandoned.The hit rate is efficiently increased because hierarchical lookups.Additionally,an original replacement policy—index aligned strategy(IndAlign_LRU) is proposed to implement least recently unused replacement policy for multiple cache line sizes.Performance evaluation indicates that the adaptive cache line scheme greatly decreases the reduction of data transfer and improves hit rate.Additionally,average execution speed of the HLSC is faster than that of the cache line design with 1024B,512B,256B and 128B by 28.9%,29.7%,32.1% and 33.5%,respectively.