Adapting an Implicit Path Delay Grading Method for Parallel Architectures

Abstract

For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault (PDF) coverage estimates, especially as a subroutine for automatic test pattern generation and timing analysis solutions. A parallel adaptation of an established framework for implicit PDF grading on with a general-purpose computing on graphics processing units (GPU) implementation is presented. Experimental evaluation on a NVIDIA Tesla C2075 GPU shows on average 50× speedup against the basic version for the framework on an Intel Xeon E5504 host system. Over a 1200× speedup is observed against a single-threaded, more complex version in the framework which grades more faults.