Adaptation of counters redundant bits with the provision of dual supply and modified clock gating to favour of low power in VLS

Abstract

The utilization of usual supply voltage and clock for repetitive state transistors in digital circuits is a fundamental driver for high power utilization. Most significant bit states of the counter stay longer than the least significant bit states and it has some repetitive states. To limit the supply voltage and stop the clock for MSB Flip Flop (FF) transistor, our method uses Control Combinational Logic, Voltage selector and Modified Integrated Clock Gating blocks. The LSB transistor always have a supply voltage of 1.2V and succession of the clock, while MSB transistor gets just 480mV and the clock will be stopped by the this technique. Bring down the supply voltage and quit the clock for redundant states either 0 or 1 in MSB. Meantime supply 1.2V and clock for state changes over from one state to next state. The experimental simulation was done in 45nm CMOS technology using Cadence virtuoso indicates that this asynchronous counter achieves a power savings of 23.57% and the same modified technique when applied to the counters with transmission-gate FF, hybrid-latch FF and sense amplifier FF will have more than 40% power savings and the technique applied in some benchmark circuits will have more than 22% power savings than existing techniques.