Achieving Zero Cache-Miss based on the Control Flow Graph

Abstract

This paper provides a design of a control circuit for cache memory with no time overhead for cache miss conditions. this type of circuits is very important in modern computers design to enhance program execution time and increase the processor performance. The main objective of the designed circuit is to provide a high performance of program execution and avoiding cache miss. The focus is on finding an optimal method that provides fast program execution. This is due to the fact that most of the existing methods are still producing cache miss. The proposed method is based on utilizing the control flow graph (CFG) of the program being executed. The proposed solution works with dividing the program into basic blocks of instructions. The program blocks and the execution paths are modeled by the CFG. A program traverses an execution path according to its current state which is represented by its data variables. If a block is required to be entered from the current block, that block is already available in the cache. This leads to eliminating cache miss. In this paper we provide the design for a cache memory control circuit that manages the cache according to the information of the CFG. Many experiments were run and tested using simulation that evaluated the proposed control circuit.