Achieving Multiple Resistance States in Phase-Change Memory Cell

Abstract

Ge2Sb2Te5 (GST)-based phase-change random access memory (PCM) cells were successfully fabricated by a standard 0.18 µm complementary metal–oxide–semiconductor (CMOS) process. The bottom electrode contacts (BECs) of the PCM cells are tungsten heaters with hollow columns filled with SiO2 and Ge. An approach of multiple resistance states (MRSs) was demonstrated. It was revealed and simulated that the observed MRS, in fact, derives from the hollow tungsten BEC architecture. The variance of electrical resistance between the MRSs can be as high as two orders. With a proposed model, our research demonstrated a simple but applicable concept of building a more stable multiple storage (MS) PCM cell by simply tuning the contact area between the BEC and GST.