Achieving High Minority Carrier Lifetime through Low-Temperature a-Si:H Deposition and High-Temperature Anneal for Silicon Heterojunction Solar Cell Applications

Abstract

The surface passivation characterized by minority carrier lifetime is a key requirement for silicon heterojunction solar cells. In this paper, we investigated how a-Si deposition temperature and post annealing influence passivation quality. The lifetime was quite low if the deposition temperature was below the typical deposition temperature T0 . While the lifetime could reach a high level after the sample was annealed at ~200ºC. This was even higher than that of the layers deposited at high temperature T0 and 1.2T0 . As silicon heterojunction solar cells have typical ~200ºC thermal processes in subsequent steps, this low-temperature a-Si deposition method may utilize these thermal processes to enhance lifetime and thus no additional annealing step is needed for cell integration. The i-aSi/c-Si interface was also characterized by TEM and FTIR spectroscopy, respectively, indicating that the lifetime degradation maybe attributed to local Si epitaxy growth and Si-H2 bonding at the i-aSi/c-Si interface.