Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth.

Abstract

As a crucial component of neuromorphic chips, on-chip memory usually occupies most of the on-chip resources and limits the improvement of neuron density. The alternative of using off-chip memory may result in additional power consumption or even a bottleneck for off-chip data access. This article proposes an on- and off-chip co-design approach and a figure of merit (FOM) to achieve a trade-off between chip area, power consumption, and data access bandwidth. By evaluating the FOM of each design scheme, the scheme with the highest FOM (1.085× better than the baseline) is adopted to design a neuromorphic chip. Deep multiplexing and weight-sharing technologies are used to reduce on-chip resource overhead and data access pressure. A hybrid memory design method is proposed to optimize on- and off-chip memory distribution, which reduces on-chip storage pressure and total power consumption by 92.88% and 27.86%, respectively, while avoiding the explosion of off-chip access bandwidth. The co-designed neuromorphic chip with ten cores fabricated under standard 55 nm CMOS technology has an area of 4.4 mm 2 and a core neuron density of 4.92 K/mm 2, an improvement of 3.39 ∼30.56× compared with previous works. After deploying a full-connected and a convolution-based spiking neural network (SNN) for ECG signal recognition, the neuromorphic chip achieves 92% and 95% accuracy, respectively. This work provides a new path for developing high-density and large-scale neuromorphic chips.