Abstract
In this paper, we present a new proven methodology, which identifies the killer defects and marginal designs by overlaying the electrical failure signatures and addresses from wafer sort to the inline defect inspection results. Not only have this new approach helped identifying killer defects that are difficult to PFA, it also benefits inspection recipe tuning and finding the root causes of different defects. This approach has been successfully implemented in 40/45nm products, and shortened the yield learn cycle significantly.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
