Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders

Abstract

Timing and area of circuits are two of the most important design criteria to be optimized in data path synthesis. In addition, carry-save-adder (CSA) has been proven to be one of the most efficient implementation units in optimizing timing and/or area of arithmetic circuits. However, the existing approaches are restricted in using CSAs, i.e., optimizing operation trees separately without any interaction between them, resulting in a locally optimized CSA circuit. To overcome this limitation, we propose a practically efficient solution to the problem of an accurate exploration of timing and area trade-offs in optimizing arithmetic circuits in the presence of multiple operation trees using CSAs. The application of our approach is able to find a best CSA implementation of circuit in terms of timing and area.