Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

Abstract

Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices results in the drastic increase of total leakage power in a logic circuit. In this paper, a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in nanoscaled bulk CMOS devices has been developed. Current models have been developed based on the device geometry, two-dimensional doping profile, and operating temperature. A circuit-level model of junction BTBT leakage has been developed. Simple models of the subthreshold current and the gate current have been presented. Also, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a sum of current sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25-nm effective length) at room and elevated temperatures.