Accurate and cost‐effective technique for jitter and noise separation based on single‐frequency measurement

Abstract

A simple and cost-effective technique is proposed for jitter and noise separation in ADC test. On the basis of the property that clock jitter is modulated by the slope of input signal, few simple mathematical manipulations are performed on a single data record of ADC output to separate jitter and noise. The proposed method requires only one high-frequency signal test and eliminates the need for a second low-frequency test in conventional dual-frequency jitter tests. Compared with existing single-frequency test, the new method is accurate and robust to non-harmonic distortion, without requiring any additional data acquisition time. Therefore, both hardware overhead and data acquisition time are saved significantly. Experimental results show that both jitter and signal-to-noise ratio are estimated accurately, and the accuracy of jitter estimation is comparable with that of conventional dual-frequency test.