Accurate analysis of parasitic current overshoot during forming operation in RRAMs

Abstract

In this paper, a peculiar attention is turned towards the understanding of the current overshoot occurring during the forming operation in resistive switching memory devices. This phenomenon is attributed to the discharge of a parasitic capacitance in parallel to the resistive device in simple 1R (one resistor, no transistor/diode selector) architectures. The impact of such an overshoot is analyzed on both NiO and HfO 2-based memory elements by performing measurements with different setups (quasi-static and pulse measurements). We show that the parasitic event is more severe as the forming voltage in the memory device increases. Moreover, it is shown that the post-forming resistance cannot be simply adjusted by a current compliance available on semiconductor parameter analyzers, since this internal limiter is ineffective in the microsecond range for compliance levels lower than the current spike. The current overshoot playing a detrimental role on the electrical performances of resistive devices, it must be carefully monitored when assessing the electrical performances in simple 1R architectures.