Abstract
Schmitt trigger (ST) circuits are widely used integrated circuit (IC) blocks with hysteretic input/output (I/O) characteristics. Like the I/O characteristics of a living neuron, STs reject noise and provide stability to systems that they are deployed in. Indeed, single-input/single-output (SISO) STs are likely candidates to be the core unit element in artificial neural networks (ANNs) due not only to their similar I/O characteristics but also to their low power consumption and small silicon footprints. This paper presents an accurate and detailed analysis and design of six widely used complementary metal-oxide-semiconductor (CMOS) SISO ST circuits. The hysteresis characteristics of these ST circuits were derived for hand calculations and compared to original design equations and simulation results. Simulations were carried out in a well-established, 0.35 μm/3.3 V, analog/mixed-signal CMOS process. Additionally, simulations were performed using a wide range of supplies and process variations, but only 3.3 V supply results are presented. Most of the new design equations provide better accuracy and insights, as broad assumptions of original derivations were avoided.
Highlights
Artificial neural networks (ANNs) are the core of artificial intelligence (AI) in generation systems that mimic the parallel processing capabilities of the human brain
Vout node voltage is close to VDD, and M3 shorts Vcn to Vn effectively connecting the gate of M5 to its drain, which keeps it in the SAT region
Hysteresis voltage as large as 1 V can be achieved by increasing all all design design parameters, this will result in a large silicon footprint
Summary
Artificial neural networks (ANNs) are the core of artificial intelligence (AI) in generation systems that mimic the parallel processing capabilities of the human brain. Detailed equations of accurately each topology are presented in Section their design limitations and sensitivities to process variations. 3, as aresingle the comparisons between hand andare theanalyzed simulation this section, providing level andcomparisons more accurate and intuitive design equations. They are results of each topology,transistor in addition to the between the six topologies.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
