Accuracy Improvement of Polynomial Computing RSFQ Circuits Based on Stochastic Computing by Partial Duplication

Abstract

This study proposes a design method for RSFQ stochastic computing (SC) circuits. The method generates circuits with improved accuracy compared to a previously proposed method. This improvement in accuracy is realized using partial duplication. SC requires a large number of clock cycles to obtain a calculation result owing to lengthy observation of the output bitstream. The proposed method can either enhance the accuracy while maintaining the latency or mitigate the latency in clock cycles while maintaining the same accuracy. The design method duplicates a small part of the original circuit considering effectiveness for accuracy improvement. Therefore, the number of additional gates in circuits designed with the proposed method is negligible. The evaluation results indicate that, compared to circuits without duplication, the mean absolute error of circuits including one duplicated part designed with the method is reduced to approximately 60%.