Abstract

Simulated annealing (SA), while being successful as a general optimization technique applicable to many modeling and design problems of microwave devices and circuits, is very time consuming. To alleviate this problem, the authors propose the creation of a hardware-implemented SA accelerator. The design and evaluation of this SA accelerator, as well as its application to the microwave computer-aided design (CAD) area, are presented. this accelerator features a highly parallel pipeline structure with a programmable characteristic function. Acceptance prediction is used to further improve the performance. Simulation results demonstrate that this accelerator has a significant (several orders of magnitude) speed advantage over an ordinary implementation. >

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