Acceleration of Nested Conditionals on CGRAs via Trigger Scheme

Abstract

Coarse-Grained Reconfigurable Architecture (CGRA) is a promising accelerator when considering both high performance and high power-efficiency. One of the challenges that CGRAs are confronting is to accelerate loops with control flow (if-then-else structures). Existing techniques employ predication to accelerate the conditionals but cannot accelerate nested conditionals efficiently. The state-of-the-art method dual issue scheme issues instructions from both the branch paths and then executes only the instructions from the path chosen by a predicate. But it also cannot handle nested conditionals. In this paper, we propose a solution to map loops with nested conditionals on a CGRA for the Triggered Instruction Architecture (TIA) paradigm - in which lacks compiler support. Experimental results show: We can accelerate loop kernels with nested conditionals via trigger scheme average of 1.41x, 1.79x and 1.29x better performance compared to partial predication, full predication and dual issue scheme respectively.