Acceleration of k-Nearest Neighbor Algorithm on FPGA using Intel SDK for OpenCL

Abstract

Field Programmable Gate Arrays (FPGAs) have been widely used for accelerating machine learning algorithms. However, the high design cost and time for implementing FPGA-based accelerators using traditional HDL-based design methodologies has discouraged users from designing FPGA-based accelerators. In recent years, a new CAD tool called Intel FPGA SDK for OpenCL (IFSO) allowed fast and efficient design of FPGA-based hardware accelerators from high level specification such as OpenCL. Even software engineers with basic hardware design knowledge could design FPGA-based accelerators. In this paper, IFSO has been used to explore acceleration of k-Nearest-Neighbor (kNN) algorithm using FPGAs. kNN is a popular algorithm used in machine learning. Bitonic sorting algorithm was used within the kNN algorithm to check if this provides any performance improvements. The experimental results obtained from FPGA-based acceleration were compared with the state of the art CPU implementation. The optimized algorithm was implemented on two different FPGAs (Intel Stratix A7 and Intel Arria 10 GX). Experimental results show that the FPGA-based accelerators provided similar or better execution time (up to 80X faster) and better power efficiency (83% reduction in power consumption) than traditional platforms such as a workstation based on two Intel Xeon processors E5-2620 Series (each with 6 cores and running at 2.4 GHz).