Acceleration of accurate floating point operations using SIMD

Abstract

Several computing systems that use decimal number calculations suffer from the accumulation and propagation of errors. Decimal numbers are represented using specific length floating point formats and hence there will always be a truncation of extra fraction bits causing errors. Several solutions had been proposed for such a problem. Among those accurate calculation systems was the usage of vectors of floating point numbers to represent decimal values with very large accuracy, known as Multi-Number System (MN). Unfortunately, MN calculations are time consuming and are not suitable for real time applications. Several attempts for special architectures had been proposed to speed up those calculations. In this work, the Single Instruction Multiple Data (SIMD) paradigm found in modern CPUs is exploited to accelerate the MN calculations. The basic arithmetic operation algorithms had been modified to utilize the SIMD architecture and a new Square representation of operands had been proposed, this representation was introduced because the MN operations are sequential and iterative, and thus we can't apply the SIMD parallel instructions directly. The proposed architecture has an execution time that is 35% of the original MN execution time for the division, which is the most time consuming operation while preserving the same accuracy.