Accelerating Seismic Computations on FPGAs – From the Perspective of Number Representations

Abstract

Conventional seismic processing is performed on a CPU with 32 or 64-bit precision for all operations. In certain cases, using a reduced precision produces equivalent result within acceptable tolerances. However, as CPUs do not support configurable bit-widths, reducing precision brings no benefits to performance. In contrast, Field Programmable Gate Arrays (FPGA) enable application specific number representations. With hardware support for reconfigurable number format and bit-width, reduced precision can greatly decrease the area cost and I/O bandwidth of the design, thus multiplying the performance with concurrent processing cores on an FPGA. In this paper, we present a tool to determine the most appropriate number format for a given seismic application. We demonstrate the methodology on a source-receiver downward continuous based migration. The acceleration device is a Maxeler Technologies MAX-1 card containing a Xilinx Virtex-4 FPGA and connects to a PC over a PCI Express bus. Using optimized number representations, we can implement two concurrent processing cores on the FPGA, and achieve a speedup of 14 times compared to a Intel Xeon 1.86GHz CPU. Moreover, with sufficient bandwidth between the CPU and FPGA, we show that a further increase to 48x speedup is possible.