Accelerating identification of custom instructions for extensible processors

Abstract

Extensible processors are increasingly becoming popular as they allow for incorporating custom instructions to meet design constraints. Identifying custom instructions is a time-consuming process particularly when large applications are considered. In this study, efficient techniques for identifying custom instruction candidates are proposed. New pruning criteria are introduced and combined with the latest work cited in the literature to accelerate the identification process. The proposed techniques have been shown to be capable of enumerating all valid patterns corresponding to given micro-architectural constraints with reduced search space. Experimental results show that, the proposed algorithm is capable of reducing the runtime by up to 50% for the case of single-output constraint, and by up to 44% for the case of multiple-output constraint. In addition, an approximation algorithm is also proposed to select the valid pattern that provides for maximum gain in execution of applications. In particular, the proposed algorithm focuses on the promising candidates, instead of enumerating all valid patterns as was the case in previous algorithms. It has been shown to be capable of obtaining the optimal valid pattern for most cases of I/O constraints and the runtime has been reduced by up to 90% for some I/O constraints.