Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory

Abstract

Field-programmable gate array (FPGA)-based ternary content-addressable memories (TCAMs) are constantly evolving in terms of hardware, power consumption, and speed. One disadvantage of these emulated TCAMs is its poor update-latency. Traditional FPGA-based TCAMs have an update-latency of N clock cycles compared to the lookup-latency of one clock cycle, where N is the depth of TCAM. Later, the update-latency is improved to t clock cycles, where t is the number of don't care bits. In this letter, we presented two mechanisms for updating FPGA-based TCAM and successfully implemented on Xilinx Virtex-6 FPGA: an accelerated MUX-Update mechanism and a cost-effective LUT-Update mechanism. MUX-Update provides an update-latency of W+1 clock cycles by using only three input/output (I/O) pins, whereas W is the width of TCAM. LUT-Update yields a constant update-latency of 2 clock cycles, independent of the size of TCAM, by using W I/O pins.