Accelerated Lifetime Testing and Analysis of Delta-Doped Silicon Test Structures

Abstract

As transistor features shrink beyond the 2 nm node, studying and designing for atomic scale effects become essential. Being able to combine conventional CMOS with new atomic scale fabrication routes capable of creating 2D patterns of highly doped phosphorus layers with atomic precision has implications for the future of digital electronics. This work establishes the accelerated lifetime tests of such doped layers, showing that these materials survive high current (>3.0 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and 300°C for greater than 70 days and are still electrically conductive. The doped layers compare well to failures in traditional metal layers like aluminum and copper where mean time to failure at these temperatures and current densities would occur within hours. It also establishes that these materials are more stable than metal features, paving the way toward their integration with operational CMOS.