Accelerated AES implementations via generalized instruction set extensions

Abstract

Efficient implementation of block ciphers is critical towards achieving both high security and high-speed processing. Numerous block ciphers, including the Advanced Encryption Standard (AES), have been proposed and implemented, using a wide and varied range of functional operations. Existing microp rocessor architectures do not provide this broad range of support. However, the advent of intellectual property (IP) processor cores presents the opportunity to augment existing datapaths with instruction set extensions to add acceleration modules in the form of new instructions. We will present a general purpose instruction set extension to a 32-bit SPARC V8 compatible processor core that accelerates the performance of Galois Field fixed field constant multiplication, a core element of the AES algorithm. This extension will be shown to accelerate AES encryption versus pure software implementations at a small hardware cost. This matches the improvement demonstrated in previously proposed AES-specific instruction set extensions while maintaining a generalized implementation format capable of supporting other algorithms that use Galois Field fixed field constant multiplication.