AC stress analysis of trench-based multi-gate transistors in a 40 nm e-NVM technology

Abstract

This work addresses the reliability of different architectures of novel high-density multi-gate transistors manufactured in a 40 nm embedded non-volatile memory process technology. The multi-gate architectures are based on lateral transistors integrated in deep trenches built alongside the main planar transistor. These architectures increase the conduction channel width with a weak impact on the footprint. A reliability study based on AC stress tests is carried out to monitor the multi-gate oxide degradation and in particular the interaction between planar and vertical oxides is highlighted. Finally, a benchmark of stress immunity, among the three studied multi-gate architectures, is presented.