Abstract: Pattern generation on wafers using the electron-beam exposure system (EBES)

Abstract

Using the electron-beam exposure system (EBES) for direct pattern generation on wafers offers the means to make circuits with feature dimensions of only a few micrometers and alignment tolerances less than 1 μm. For such a program to be successful, techniques had to be developed to (a) rapidly register the pattern, (b) minimize the writing time, and (c) pattern the various thin films used in circuit fabrication. For pattern registration, EBES need only determine the positions of three nonlinear fiducial marks which form a triangle spanning most of the wafer area. The position data are used to calculate the translation, rotation, skew, and magnification required to get the best fit of the old pattern to the new. The corrections are applied to the electron-beam writing operation. It takes less than two minutes to register an entire 2-in. (5.08-cm) wafer to within a ±1/2-μm accuracy. The writing time is usually less than 20 min to expose all the chips fully covering a 2-in. (5.08-cm) Si wafer, even when there are three or four different types of circuit on the wafer. This can be achieved by laying out the chips to specifically match the EBES writing characteristics. The resist used has been poly (glycidyl methacrylate-co-ethyl acrylate), a sensitive negative electron resist. Techniques were devised to etch patterns on many different substrates following resist development. For pattern generation on Si wafers, the substrates included thin films of SiO2 (thermally grown as well as CVD), Si3N4, W, polysilicon, Al, and Ti–Pd–Au (see Table I). Subsequently, MOS circuits were made with combinations of the above techniques. These circuits2 include 1024-bit RAM’s, some with 5.5-μm gates, 3.0-μm contact holes, and 4.5-μm interconnecting metallization. Also, inverters, as well as discrete IGFET’s with gate lengths varying from 2 to 12 μm, were made. EBES has also been used to delineate the thin film patterns required for GaAs MES FET fabrication (see Table II). Some devices have up to fourteen 2.5-μm gates with 2.5-μm gate-to-source spacings while others have single 2.0×500-μm gates with 2.0-μm spacings. These devices require alignment better than ±0.25 μm and metal conductors with thickness-to-width ratios as high as 1/2. Single gate MES FET’s made in this way have values of transconductance of up to 25 mmhos.