Abstract

In this work we examine the problem of regulating available bit rate (ABR) traffic in an ATM network. The issue of providing control signals to throttled sources at distant locations from a bottlenecked node is of particular interest. The process of modeling and design of the controller is outlined. A linear quadratic tracker is used to provide the appropriate control signal to each source. It is shown that designing the controller for minimum error energy resulted in the best tracking performance. However this result is obtained at the expense of VC buffer time delays. This situation is remedied by the addition of a simple regulator. Using a regulator one can obtain low buffer overshoot in the transient period while maintaining the good link utilization in the steady-state period.

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