About electrical properties of passivated SiO2/Si structures prepared electro-chemically in HClO4 solutions

Abstract

The contribution mainly presents results obtained on passivated SiO2/Si structures prepared in HClO4 solutions. The cleaned Si (100) wafers were immersed in 1M HClO4 aqueous solutions and oxidized under positive bias. Results obtained on wet chemically prepared SiO2/Si structures are compared with corresponding ones obtained on MOS formed by thermal oxidation at 850°C. Resulting oxide thicknesses of the layer prepared by electrochemical and thermal manners are ∼15nm and ∼7.5nm, respectively. All of prepared SiO2/Si structures were passivated in HCN or KCN solutions. Low density of interface defect states below the level of ∼1011eV−1cm−2 was determined on structures with the SiO2 layer prepared electrochemically, passivated in aqueous HCN solutions, and annealed in vacuum at low temperatures. It has been shown that residual interface electron traps detected by Q-DLTS or C–V method after passivation procedures on electrochemically prepared samples can be partly transformed to mobile and/or immobile charged particles which shift the flat-band voltage of MOS and increase the magnitude of hysteresis of C–V curves.