Abstract
针对目前数字音频广播(DAB)收音机中DSP软件AAC+解码器功耗大的问题，该文提出了低功耗AAC LC解码器的ASIC设计，以极低的硬件代价完成了最基本的DAB+节目解码，加入DAB解码芯片后巧妙地实现了DAB+和DAB两种不同标准的兼容。该文设计优化了反量化与IMDCT算法，使用了分时工作法，从而实现了低功耗。该设计的系统时钟为16.384 MHz，采用0.18 m CMOS工艺，功耗约为6.5 mW，并与DAB信道解码结合，通过了FPGA开发板上的实时验证，且完成了芯片的版图设计，芯片面积为14 mm2。
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