A yield prediction model and cost of ownership for productivity enhancement beyond imec 5nm technology node

Abstract

In semiconductor manufacturing, yield and cost are important factors to predict and improve the productivity of manufactures. A yield prediction model and the corresponding cost of the ownership with advanced technology nodes beyond imec 5nm are proposed in this paper. In this study, the compact die yield data and the cost will be compared between imec 8nm, 7nm and 5nm technology nodes. With technology nodes scaling, the node-to-node scalability can be impacted by the process complexity, different number of layers, and chip size, etc. With proper process parameters, the yield per layer and the yield per chip can be extracted. In addition, the productivity and turn-around-time (TAT), also called cycle time (CT), can also be calculated based on yield and cost model with complex manufacturing process steps to improve the manufacturability and turnaround-time (TAT). The productivity can be easily evaluated by the yield prediction model since productivity and yield are inseparable in manufacturing. Based on the process assumption, the turn-around-time (TAT) can be precisely estimated by the result of the wafer process time including the time of each step provided by the imec database. As the scaling persists, growing complexity in semiconductor manufacturing gives rise to a concern on the yield and cost. We studied a yield model and the corresponding cost of the ownership for imec technology nodes to discuss their manufacturability. With technology nodes progression, the node-to-node scalability is shown to be impacted by the process complexity from the number of layers, patterning methods and chip size, etc. In addition, productivity and turn-aroundtime (TAT), also referred as the cycle time (CT), can also be estimated to be used as an important parameter to enhance productivity and optimize profitability in semiconductor manufacturing.