A Workstation-Based Mixed Mode Circuit Simulator

Abstract

A new mixed mode simulator is described, which combines a behavioral timing simulator, a switch level simulator, and a new circuit-level simulator based upon the ADEPT timing simulation algorithm. These simulation algorithms are combined into a single, consistent, interactive MOS simulator. In addition, STAFAN fault simulation is provided at the transistor level to grade vectors to be used in the testing phase of design. In this paper, each algorithm is described as well as the interfacing required between each of the simulation methods. Several examples are presented to demonstrate the utility of the L-Simulator. Circuit simulation is performed on a wide range of CMOS counter sizes, from 2 to 32 bits, showing tremendous reductions in CPU time as compared to SPICE, without loss in accuracy. A novel multi-mode simulation facility is also introduced, further decreasing the CPU time requirements for simulation. A second example shows how the performance and area of a CMOS latch is optimized using circuit modification techniques during simulation. Finally, a 73,200 transistor design of an 8051-like CPU is simulated in behavioral, switch level, and finally in circuit/mixed modes.