A WIP Balancing Procedure for Throughput Maximization in Semiconductor Fabrication

Abstract

In a semiconductor fabrication line (fab), high throughput often guarantees high revenue and profit since relatively constant operating cost is required throughout the year; however, maintaining high throughput has been a challenging task due to complicated operational variables in a modern high-end wafer fabrication line. To deal these variables, the industry has developed a fab scheduling system consisting of several functional modules that focus on different areas of decision making. WIP balancing, which aims to prevent starvation of bottleneck toolsets, has been an important component for fab scheduling. This research proposes a new WIP balancing concept, which directly considers load levels of bottleneck toolsets for higher throughput. Also, an MIP (mixed integer programming) model is developed for the new WIP balancing. A performance test shows that the new approach increases throughput, especially when WIP level and product routing flexibility are low.