Abstract
A wideband triple-stacked CMOS distributed power amplifier (DPA) is implemented using a commercial 65-nm CMOS process. To enhance the output power, a triple-stacked field effect transistor (FET) is used as a gain cell in the DPA. Double inductive peaking, in which inductors are inserted at each gate and each interstage of the gain cells, is used to enhance the gain bandwidth. By analyzing the trans-conductance characteristics in the triple-stacked gain cell, interstage inductive peaking (IIP) is used to boost the gain in the mid-band frequency, and gate-inductive peaking (GIP) is used to extend the gain bandwidth in the high-edge frequency. The proposed double inductive peaking ideally enables the gain bandwidth of triple-stacked DPAs to increase from 22 to 44 GHz. The proposed DPA obtains a measured power gain of 11–15.7 dB and a measured output power of 12.8–21.7 dBm from dc to 38 GHz.
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