Abstract
The performance of a sigma-delta ADC can be increased by increasing one or more of the main three parameters, over-sampling ratio, the order of the modulators and the number of bits used. Increasing each of these parameters presents a degree of challenge (i.e., the increase in the over-sampling ratio is limited by the technology and the power consumption requirement). This paper presents a new method to obtain 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order noise shaping from two 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> order, time interleaved modulators by applying cross-coupling of quantization noise between the two paths. The proposed sigma- delta ADC is implemented in 90 nm CMOS technology.
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