A Wideband 180-GHz Phase-Locked-Loop Based MSK Receiver

Abstract

A 180 GHz mixer-first phase-locked-loop based MSK receiver is demonstrated in 65-nm CMOS. Double balanced anti-parallel-diode-pair (APDP) based sub-harmonic mixer forms the phase detector. Compensation using multiple zeros reduces the effect of in-loop delay on the stability of PLL. Without external LO synchronization, the receiver achieves 10 Gbps with a BER < 10−12 at -24-dBm available input power. The open loop measurements show the down-conversion chain has a 3-dB bandwidth of approximately 48 GHz at 180 GHz and the minimum single side band (SSB) noise figure of 18.6 dB. This receiver is the self-synchronized receiver using coherent detection with the highest operating frequency in CMOS. This work also demonstrates that a PLL based receiver can support data rates in excess of 10 Gbps.