A Wide Tuning Range Delay Element for Event-Driven Processing of Low-Frequency Signals in 28-nm FD-SOI CMOS

Abstract

This letter presents a widely tunable digital delay element suitable for low-power low-frequency continuous-time digital signal processing systems. The design uses features of the 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology to precisely control currents in the pA range and significantly reduce the leakage power. The measured tuning range is significantly larger than prior art covering more than 3 decades from 30 ns to 100 $\mu \text{s}$ making it suitable for CT-DSP low-frequency filters. At 0.7-V supply voltage, the dynamic power consumption is 15 fJ/event with a residual power consumption due to leakage of 14 pW.