Abstract

A phase-locked loop (PLL) along with a linear phase interpolator that generates 64 phases with low jitter in a continuous lock range of 400 MHz–2.2 GHz for mobile memory interfaces is presented. To provide adaptive and precise phase interpolation (PI), a novel frequency tracking PI bias along with a wide-frequency range PLL and lock-detection control are employed. The PLL-based PI is fabricated in 65-nm CMOS and achieves a peak-to-peak and an RMS jitter of 14.8 ps and 2.16 ps, respectively. The measured DNL and INL of the proposed PI are 0.21 LSB and 0.43 LSB, respectively. The PLL-based PI consumes 8.1 mW at a 1.0-V supply.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.