Abstract
This letter presents an improved architecture of wide division ratio range programmable frequency divider with driving-capability improved. The proposed architecture combines the traditional 2/3 cells and the revised ones to retain the high speed feature and broaden the output duty-cycle. Only less OR and AND gates are added to select the proper output. All of the added circuits are operating at the lower frequency. Thus it enhances the divider’s driving-capability with almost adding no power consumption. This improvement makes it applicable to drive various clocked circuits, which need different frequencies. The presented equation can be used to predict the output duty-cycle with the expected division ratio accurately. Test results show that the output duty-cycle is between 33 and 66%, which corroborate the calculations.
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