A W-Band Low-Noise PLL With a Fundamental VCO in SiGe for Millimeter-Wave Applications

Abstract

A W-band fundamental phase-locked loop (PLL) is designed and fully integrated to achieve high output power and low noise in a 0.13-μm SiGe BiCMOS process. A PLL with a fundamental voltage-controlled oscillator (VCO) is chosen after comparing several frequency-synthesizer architectures. Local oscillator (LO) generation and LO distribution are also considered. The employed free-running VCO achieves a tuning range from 92.5 to 102.5 GHz (8.3%), an output power of 6 dBm, and a phase noise of -124.5 dBc/Hz at 10-MHz offset. The locking range of the PLL is from 92.7 to 100.2 GHz, and the phase noise is -102 dBc/Hz at 1-MHz offset. The root mean square jitter integrated from 1 MHz to 1 GHz is 71 fs. Finally, the figure-of-merit for VCOs is discussed.