A wafer-level approach to device lifetesting

Abstract

An innovative wafer-level methodology is introduced and used to determine the thermal activation energies of TriQuint semiconductor’s TQPED devices. Activation energies of 2.77 eV and 2.44 eV are calculated for the depletion-mode and enhancement-mode devices, respectively. This accelerated lifetest technique utilizes a special reliability test structure that includes an on-wafer heating element around the device under test (DUT). The heating element easily achieved temperature above 275 °C without the need to bias the device. This allows the exclusive study of thermally activated failure mechanisms. The special reliability test structure allows the stressing of individual devices at different temperatures on the same wafer. This built-in flexibility allows for a fast and efficient means of evaluating device reliability by eliminating packaging overhead and considerations. In wafer form it becomes possible to spatially map the reliability of devices under test. It is also easier to observe the physical degradation of devices and determine the failure mechanisms.