A W-Band LNA/Phase Shifter With 5-dB NF and 24-mW Power Consumption in 32-nm CMOS SOI

Abstract

This paper presents a W-band phased array receive front end in 32-nm CMOS silicon-on-insulator technology. The architecture is based on cascode low-noise amplifiers and passive switched LC 5-bit phase-shifters and with root-mean-square (rms) phase error of <;3.5° at 88-93 GHz. The 4-bit equivalent (11°) rms phase error bandwidth is 88-98 GHz. An average system noise figure (NF) of 5.3 dB is obtained at 93-97 GHz with 18-dB gain and input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of -25 dBm. The low-noise amplifier and phase-shifter front end consumes 24.3 mW including bias circuits. To the author's knowledge, the front-end NF and power consumption are state of the art for silicon-based phased array receivers at W-band frequencies, and compares well with indium phosphide (InP) and gallium arsenide (GaAs) pseudomorphic high electron mobility transistor front ends.