Abstract
The single-chip implementation of a general-purpose fuzzy logic inference engine is described. Features include a dynamically reconfigurable and cascadable architecture, TTL (transistor-transistor logic)-compatible host interface, laser-programmed redundancy, special mode for testability, RAM rule storage, and on-chip fuzzification and defuzzification. Up to 102 parallel rules can be processed in real-time control applications by utilizing a 1-mm, 3.3-V DLM CMOS technology. 580 KFLIPS (fuzzy logic inferences per second) are attained using 688 K transistors and 36-MHz operation
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
