A VLSI design for fast vector normalization

Abstract

The design of a vector normalizer is described. It is an integral part of our graphics subsystem for scientific visualization, but will be of great use for speeding up any computer graphics architecture. In the actual design, the circuitry handles 3D-vectors with 33 bit two's complement components. The components of the normalized vectors are computed as 16 bit two's complement fixed-point numbers. Due to the overall pipeline architecture, the chip accepts one 3D-vector and produces one normalized vector each clock. To normalize a 3D-vector, three square operations, two additions, one square root operation and three divisions must be performed. The target clock frequency is 50 MHz, by which the performance of the chip rates at 450 MOPS. A single-chip VLSI implementation is currently in work, simulation results will be available by the end of the third quarter '93. We use Mentor 8.2 tools on HP 700 workstations and Toshiba's TC160G Gate Array technology.