Abstract
The authors present three VLSI chips-a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip-for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as PROLOG. The CU chip implements a hardware support called 'trial buffer' which is suitable for the execution of the PROLOG-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a PROLOG-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384000 transistors is fabricated in a 0.8 mu m double-metal CMOS technology. The CU chip and the NU chip contain 610000 and 329000 transistors, respectively. They are fabricated in a 1.0 mu m double-metal CMOS technology. A cell-based design method is used to reduce the layout design time. >
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