A VLSI architecture for dynamic scene analysis

Abstract

Analysis of dynamic scenes to obtain motion parameters, structures and identities of the objects present in the scene and/or descriptions of the events taking place in the scene is an important problem in machine vision. Dynamic scene analysis involves processing and analysis of a sequence of image frames (snapshots of the scene) taken at a regularly spaced time interval. Since a large volume of data is to be processed, dynamic scene analysis techniques are, in general, computationally very intensive which makes them unsuitable for applications which require real-time response. A common approach to obtaining motion related information about a scene involves analyzing the characteristics of the connected regions in the corresponding difference pictures. Previous implementations of the difference-picture-based technique use multicomputer and multiprocessor systems which are uneconomical because of the overheads involved. In this paper, we propose a VLSI architecture that exploits the pipelining and the parallelism possible in the above technique. Each processor is organized as a multistage linear pipeline and the processor architecture is simple enough that the motion detection and classification system can be implemented as a single VLSI chip. Once the difference picture has been generated and segmented into separate regions corresponding to motions of different objects, each processor in our proposed chip will independently analyze a different region to classify the type of motion occuring in that region within the scene. Currently, the processor architecture is being laid out in silicon at the University of South Florida for actual fabrication and testing. The chip is expected to operate at the rate of 20 MHz.